Typical test methodologies rely on external data to set up corner case interactions, which extensively covers more accessible logic while infrequently covering many deeply-seeded internal states. A rare corner case cause by the simultaneous occurrence of a relatively small number of common internal states may take weeks or even months to hit during post-silicon testing and may even take years if another condition is added. This problem worsens with increased internal complexity and decreased interfaces due to increased integration. All of this makes highly integrated circuit designs progressively susceptible to silicon escapes.